The CDCM7005 provides high-precision, stable frequency for signal chain devices such as analog-to-digital converters (ADCs), digital-to-analog converters (DACs), digital upconverters (DUCs), and digital downconverters (DDCs). At the same time, the device features industry-lowest phase noise of -219dBc/Hz (PLL quality factor), 162fs for LVPECL, and minimum phase jitter performance of 232fs for LVCMOS, and a maximum output offset of 20ps. This performance not only undersamples data converters such as ADCs at higher input frequencies, but also provides the highest signal-to-noise ratio.
The CDCM7005 has features that maximize design flexibility, including Serial Peripheral Interface (SPI) logic for programming and independent support control. The device synchronizes the voltage controlled crystal oscillator (VCXO) frequency up to 2.2 GHz (LVPECL) with either of the two reference clocks to provide a clean high frequency clock output. These outputs can be divided by a ratio of 1, 2, 3, 4, 6, 8, or 16 and provide LVCMOS and LVPECL level output options.
The solution also has other features, including a device bias voltage (VBB) pin that provides the correct voltage for a single-ended VCXO, eliminating the need for external resistors and significantly simplifying the product design process. In addition, the CDCM7005 supports frequency hold mode and fast frequency lock for auto-protection and higher system redundancy.
The 3.3V CDCM7005 is available now and can be ordered through TI and its authorized distributors. The device has an industrial temperature range of -40°C to 85°C and is available in a 64-pin, 0.8mm BGA and 48-pin 0.5mm QFN package. The suggested retail price is $10.75 in 1,000-piece quantities. The evaluation board has also been released simultaneously.
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